1 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wv3eg265m64efsu-d4 october 2005 rev. 1 1gb C 2x64mx64 ddr sdram unbuffered, w/pll features double-data-rate architecture pc2700 and pc2100 bi-directional data strobes (dqs) differential clock inputs (ck & ck#) programmable read latency 2, 2.5 (clock) programmable burst length (2,4,8) programmable burst type (sequential & interleave) auto and self refresh, (8k/64ms refresh) serial presence detect with eeprom power supply: v cc /v ccq : 2.5v 0.2v dual rank 200 pin so-dimm package ? package height options: d4: 31.75 mm (1.25) note: consult factory for availability of: ? rohs compliant products ? vendor source control options ? industrial temperature option description the wv3eg265m64efsu is a 2x64mx64 double data rate sdram memory module based on 512mb ddr sdram component. the module consists of sixteen 64mx8 bit with 4 banks ddr sdrams in fbga packages mounted on a 200 pin substrate. synchronous design allows precise cycle control with the use of system clock. data i/o transactions are possible on both edges and burst lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system ap pli ca tions. * this product is subject to change without notice. operating frequencies ddr333 @cl=2.5 ddr266 @cl=2 ddr266 @cl=2.5 clock speed 166mhz 133mhz 133mhz cl-t rcd -t rp 2.5-3-3 2-2-2 2.5-3-3
2 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wv3eg265m64efsu-d4 october 2005 rev. 1 pin configuration pin# symbol pin# symbol pin# symbol pin# symbol 1v ref 51 v ss 101 a9 151 dq42 2v ref 52 v ss 102 a8 152 dq46 3v ss 53 dq19 103 v ss 153 dq43 4v ss 54 dq23 104 v ss 154 dq47 5 dq0 55 dq24 105 a7 155 v cc 6 dq4 56 dq28 106 a6 156 v cc 7dq157v cc 107 a5 157 v cc 8dq558v cc 108 a4 158 nc 9v cc 59 dq25 109 a3 159 v ss 10 v cc 60 dq29 110 a2 160 nc 11 dqs0 61 dqs3 111 a1 161 v ss 12 dm0 62 dm3 112 a0 162 v ss 13 dq2 63 v ss 113 v cc 163 dq48 14 dq6 64 v ss 114 v cc 164 dq52 15 v ss 65 dq26 115 a10 165 dq49 16 v ss 66 dq30 116 ba1 166 dq53 17 dq3 67 dq27 117 ba0 167 v cc 18 dq7 68 dq31 118 ras# 168 v cc 19 dq8 69 v cc 119 we# 169 dqs6 20 dq12 70 v cc 120 cas# 170 dm6 21 v cc 71 nc 121 cs0# 171 dq50 22 v cc 72 nc 122 cs1# 172 dq54 23 dq9 73 nc 123 nc 173 v ss 24 dq13 74 nc 124 nc 174 v ss 25 dqs1 75 v ss 125 v ss 175 dq51 26 dm1 76 v ss 126 v ss 176 dq55 27 v ss 77 nc 127 dq32 177 dq56 28 v ss 78 nc 128 dq36 178 dq60 29 dq10 79 nc 129 dq33 179 v cc 30 dq14 80 nc 130 dq37 180 v cc 31 dq11 81 v cc 131 v cc 181 dq57 32 dq15 82 v cc 132 v cc 182 dq61 33 v cc 83 nc 133 dqs4 183 dqs7 34 v cc 84 nc 134 dm4 184 dm7 35 ck0 85 nc 135 dq34 185 v ss 36 v cc 86 nc 136 dq38 186 v ss 37 ck0# 87 v ss 137 v ss 187 dq58 38 v ss 88 v ss 138 v ss 188 dq62 39 v ss 89 nc 139 dq35 189 dq59 40 v ss 90 v ss 140 dq39 190 dq63 41 dq16 91 nc 141 dq40 191 v cc 42 dq20 92 v cc 142 dq44 192 v cc 43 dq17 93 v cc 143 v cc 193 sda 44 dq21 94 v cc 144 v cc 194 sa0 45 v cc 95 cke1 145 dq41 195 scl 46 v cc 96 cke0 146 dq45 196 sa1 47 dqs2 97 nc 147 dqs5 197 v ccspd 48 dm2 98 nc 148 dm5 198 sa2 49 dq18 99 a12 149 v ss 199 nc 50 dq22 100 a11 150 v ss 200 nc pin description a0-a12 address input (multiplexed) ba0-ba1 bank select address dq0-dq63 data input/output dqs0-dqs7 data strobe input/output ck0, ck0# clock input cke0, cke1 clock enable input cs0#, cs1# chip select input ras# row address strobe cas# column address strobe we# write enable dm0-dm7 data-in mask v cc power supply (2.5v) v ccq power supply for dqs (2.5v) v ss ground v ref power supply for reference v ccspd serial eeprom power supply (2.3v to 3.6v) sda serial data i/o scl serial clock sa0-sa2 address in eeprom nc no connect
3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wv3eg265m64efsu-d4 october 2005 rev. 1 functional block diagram cs1# cs0# dqs0 dm0 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 ras# ras#: ddr sdrams cas# cas#: ddr sdrams we# we#: ddr sdrams cs1# cs1#: ddr sdrams cs0# cs0#: ddr sdrams a0-a12 a0-a12: ddr sdrams ba0-ba1 ba0-ba1: ddr sdrams s0# dqs dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 s1# dqs dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs4 dm4 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 s0# dqs dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 s1# dqs dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs1 dm1 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 s0# dqs dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 s1# dqs dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs5 dm5 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 s0# dqs dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 s1# dqs dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs2 dm2 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 s0# dqs dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 s1# dqs dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs6 dm6 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 s0# dqs dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 s1# dqs dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs3 dm3 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 s0# dqs dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 s1# dqs dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs7 dm7 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 s0# dqs dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 s1# dqs dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 serial pd scl wp sa0 sa1 sa2 a0 a1 a2 sda ddr sdrams ddr sdrams v ccspd v cc /v ccq v ref v ss ddr sdrams spd ck0 ck0# pll ddr sdrams ddr sdrams ddr sdrams ddr sdrams note: all datalines are terminated through a 22 ohm series resistor
4 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wv3eg265m64efsu-d4 october 2005 rev. 1 absolute maximum ratings parameter symbol value units voltage on any pin relative to v ss v in , v out -0.5 to 3.3 v voltage on v cc supply relative to v ss v cc -1.0 to 3.6 v voltage on v ccq supply relative to v ss v ccq -1.0 to 3.6 v storage temperature t stg -55 to +150 c operating temperature t a 0 to +70 c power dissipation p d 16 w short circuit current i os 50 ma note: permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommended operating condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability. dc characteristics 0c t a 70c, v cc = 2.5v 0.2v parameter symbol min max unit note supply voltage ddr266/ddr333 (nominal v cc of 2.5v) v cc 2.3 2.7 i/o supply voltage ddr266/ddr333 (nominal v cc of 2.5v) v ccq 2.3 2.7 v i/o reference voltage v ref 0.49*v ccq 0.51*v ccq v1 i/o termination voltage v tt v ref -0.04 v ref +0.04 v 2 input logic high voltage v ih (dc) v ref +0.15 v ccq +0.30 v input logic low voltage v il (dc) -0.3 v ref -0.15 v input voltage level, ck and ck# v in (dc) -0.3 v ccq +0.30 v input differential voltage, ck and ck# v id (dc) 0.3 v ccq +0.60 v 3 input crossing point voltage, ck and ck# v ix (dc) 0.3 v ccq +0.60 v input leakage current addr, cas#, ras#, we# i i -32 32 ua cs#, cke -16 16 ua ck, ck# -10 -10 ua dm -4 4 ua output leakage current i oz -10 10 ua output high current (normal strengh); v out = v +0.84v i oh -16.8 ma output high current (normal strengh); v out = v tt -0.84v i ol 16.8 ma output high current (half strengh); v out = v tt +0.45v i oh -9 ma output high current (half strengh); v out = v tt -0.45v i ol 9ma notes: 1. v ref is expected to be equal to 0.5*v ccq of the transmitting device, and to track variations in the dc level of the same. peak to peak noise on v ref may not exceed 2% of the dc value 2. v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref , and must track variations in the dc level of v ref 3. v id is the magnitude of the difference between the input level on ck and the input level on ck#. capacitance v cc = 2.5v, v ccq = 2.5v, t a = 25c, f = 1mhz parameter symbol min max unit input capacitance (a0-a12, ba0-ba1, ras#, cas#, we#) c in1 28 44 pf input capacitance (cke0, cke1) c in2 16 24 pf input capacitance (cs0#, cs1#) c in3 16 24 pf input capacitance (clk0, clk0#) c in4 6 7.5 pf input capacitance (dm0-dm7) c in5 11 13 pf data and dqs input/output capacitance (dq0-dq63) c out1 11 13 pf
5 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wv3eg265m64efsu-d4 october 2005 rev. 1 i dd specifications and test conditions recommended operating conditions, 0c t a 70c, v ccq = 2.5v 0.2v, v cc = 2.5v 0.2v parameter symbol conditions ddr333 @ cl = 2.5 ddr266 @ cl = 2 ddr266 @ cl = 2.5 unit operating current i dd0* one device bank active; active-precharge; t rc = t rc(min) ; t ck = t ck(min) ; dq, dm and dqs inputs change once per clock cycle; address and control inputs change once every two clock cycles 136012401240ma operating current i dd1* one device bank; active-read-precharge; bl = 4; t rc = t rc(min) ; t ck = t ck(min) ; i out = 0ma; address and control inputs change once per clock cycle 1600 1480 1480 ma percharge power- down standby current i dd2p** all device banks are idle; power-down mode; t ck = t ck(min) ; cke = low 360 360 360 ma idle standby current i dd2f** cs# = high; all device banks are idle; t ck = t ck(min) ; cke = high; address and other control inputs changing once per clock cycle. v in = v ref for dq, dqs and dm 1000 920 920 ma active power-down standby current i dd3p** one device bank active; power-down mode; t ck = t ck(min) ; cke = low 840 760 760 ma active standby current i dd3n** cs# = high; cke = high; one device bank active; t rc = t ras(max) ; t ck = t ck(min) ; dq, dm and dqs inputs change twice per clock cycle; address and other control inputs changing once per clock cycle 1080 1000 1000 ma operating current i dd4r* burst = 2; reads; continuous burst; one device bank active; address and other control inputs changing once per clock cycle; t ck = t ck(min) ; i out = 0ma 1640 1480 1480 ma operating current i dd4w* burst = 2; writes; continuous burst; one device bank active; address and other control inputs changing once per clock cycle; t ck = t ck(min) ; dq, dm and dqs inputs change twice per clock cycle 1720 1400 1400 ma auto refresh current i dd5** t rc = t rfc(min) 4920 4760 4760 ma self refresh current i dd6** cke < 0.2v 360 360 360 ma orerating current i dd7* four device bank interleaving reads burst = 4 with auto precharge; t rc = t rfc(min) ; t ck = t ck(min) ; address and control inputs change only during active read, or write commands 3560 3120 3120 ma note: i dd speci? cation is based on micron components. other dram manufacturers speci? cation may be different. * value calculated as one module rank in this operating condition and all other module ranks in i dd2p (cke low) mode. ** value calculated re? ects all module ranks in this operating condition. ac operating test conditions parameter/condition symbol min max unit input high (logic 1) voltage v ih(ac) v ref +0.31 v input low (logic 0) voltage v il(ac) v ref -0.31 v input differential voltage, ck and ck# inputs v id(ac) 0.7 v ccq +0.6 v input crossing point voltage, ck and ck3 inputs v ix(ac) 0.5*v ccq -0.2 0.5*v ccq +0.2 v
6 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wv3eg265m64efsu-d4 october 2005 rev. 1 ac timing parameters 0 t a 70c, v cc = 2.5v, v ccq = 2.5v parameter symbol 335 262 265 unit min max min max min max row cycle time t rc 60 65 65 ns refresh row cycletime t rfc 72 75 75 ns row active time t ras 42 70k 40 120k 40 120k ns ras# to cas# delay t rcd 15 20 20 ns row precharge time t rp 15 20 20 ns row active to rowactivedelay t rrd 12 15 15 ns write recovery time t wr 15 15 15 ns last data into read command t wtr 111ns clock cycle time cl=2.0 t ck 7.5 13 7.5 13 10 13 ns cl=2.5 6 13 7.5 13 7.5 13 ns clock high leve width t ch 0.45 0.55 0.45 0.55 0.45 0.55 tck clock low level width t cl 0.55 0.55 0.55 0.55 0.55 0.55 tck dqs-out access time from ck/ck# t dqsck -0.6 +0.6 -0.75 +0.75 -0.75 +0.75 ns output data access time from ck/ck# t ac -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 ns data strobe edge to ouput data edge t dqsq 0.45 0.5 0.5 ns read preamble t rpre 0.9 1.1 0.9 1.1 0.9 1.1 tck read postamble t rpst 0.4 0.6 0.4 0.6 0.4 0.6 tck ck to valid dqs-in t dqss 0.75 1.25 0.75 1.25 0.75 1.25 tck dqs-in setup time t wpres 000ns dqs-in hold time t wpre 0.25 0.25 0.25 tck dqs falling edge to ck rising-setup time t dss 0.2 0.2 0.2 tck dqs falling edge from ck rising-hold time t dsh 0.2 0.2 0.2 tck dqs-in high level width t dqsh 0.35 0.35 0.35 tck dqs-in low level width t dqsl 0.35 0.35 0.35 tck address and control input setup time (fast) t is f 0.75 0.9 0.9 ns address and control input hold time (fast) t ish f 0.75 0.9 0.9 ns address and control input setup time (slow) t is s 0.8 1 1 ns address and control input hold time (slow) t ih s 0.8 1 1 ns data-out high impedence time from ck/ck# t hz +0.7 +0.75 +0.75 ns data-out low impedence time from ck/ck# t lz -0.7 -0.75 -0.75 ns note: ac timing parameters are based on micron components. other dram manufacturers parameters may be different.
7 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wv3eg265m64efsu-d4 october 2005 rev. 1 ac timing parameters (continued) 0 t a 70c, v cc = 2.5v, v ccq = 2.5v parameter symbol 335 262 265 unit min max min max min max mode register set cycle time t mrd 10 10 10 ns dq & dm setup time to dqs t ds 0.45 0.5 0.5 ns dq & dm hold time to dqs t dh 0.4 0.5 0.5 ns control & address input pulse width t ipw 2.2 2.2 2.2 ns dq & dm input pulse width t dipw 1.75 1.75 1.75 ns exit self refresh to non-read command t xsnr 75 75 75 ns exit self refresh to read command t xsrd 200 200 200 t ck refresh interval time t refi 7.8 7.8 7.8 us output dqs valid window t qh t hp - t qhs t hp - t qhs t hp - t qhs ns clock half period t hp t cl min or t ch min t cl min or t ch min t cl min or t ch min ns data hold skew factor t qhs 0.55 0.75 0.75 ns dqs write postamble time t wpst 0.4 0.6 0.4 0.6 0.4 0.6 ns active to read with auto precharge command t rap 15 20 20 ns auto precharge write recovery + precharge time t ral (t wr /t ck ) + (t rp /t ck ) (t wr /t ck ) + (t rp /t ck ) (t wr /t ck ) + (t rp /t ck ) t ck
8 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wv3eg265m64efsu-d4 october 2005 rev. 1 67.60 (2.661) 63.60 (2.504) 1.0 0.1 (0.04 0.0039) 3.80 (0.150) max. 2.15 (0.085) 6.0 0.236 4.20 (0.165) 1.8 (0.071) 4.00 (0.158) min. 47.40 (1.866) 2- 1.80 (0.071) 11.40 (0.449) 13941 199 31.75 (1.25) full r 2x 2.40 (0.094) 4.00 0.10 (0.158 0.039) 20 (0.787) 2.45 (0.098) 4.00 0.10 (0.158 0.039) 1.00 0.1 (0.04 0.0039) 0.45 0.03 (0.018 0.001) 0.60 (0.024) 2.55 min (0.102 min) 0.25 (0.01) ordering information for d4 part number speed cas latency t rcd t rp height* wv3eg265m64efsu335d4-x 166mhz/333mb/s 2.5 3 3 31.75mm (1.25") wv3eg265m64efsu262d4-x 133mhz/266mb/s 2 2 2 31.75mm (1.25") wv3eg265m64efsu265d4-x 133mhz/266mb/s 2.5 3 3 31.75mm (1.25") notes: ? consult factory for availability of rohs compliant products. (g = rohs compliant) ? vendor speci? c part numbers are used to provide memory components source control. the place holder for this is shown as lo wer case -x in the part numbers above and is to be replaced with the respective vendors code. consult factory for quali? ed sourcing options. (m = micron, s = samsung & consul t factory for others) ? consult factory for availability of industrial temperature (-40c to 85c) option * all dimensions are in millimeters and (inches) package dimensions for d4 tolerances: 0.15 (0.006) unless otherwise speci? ed
9 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wv3eg265m64efsu-d4 october 2005 rev. 1 part numbering guide wv 3 e g 265m 64 e f s u xxx d4 -x g wedc memory ddr gold depth (dual rank) (5 = pll) bus width x8 fbga 2.5v unbuffered speed (mhz) package 200 pin component vendor name (m = micron) (s = samsung) g = rohs compliant
10 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wv3eg265m64efsu-d4 october 2005 rev. 1 document title 1gb C 2x64mx64 ddr sdram unbuffered, w/pll revision history rev # history release date status rev 0 initial release 8-05 preliminary rev 1 moved from preliminary to final 10-05 final
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